1. Field of the Invention
The present invention relates to a clock recovery apparatus for recovering a clock signal used to reproduce digital data from an incoming signal.
2. Description of the Background Art
In a signal reproduction apparatus for reproducing digital data from an incoming signal, a clock recovery apparatus for recovering a clock signal synchronized with the reproduced digital data is incorporated therein. In the signal reproduction, the incoming signal is exemplarily sampled with a timing of the recovered clock signal. Hereinafter, a clock signal suitable for reproducing digital data, in other words, an ideal clock signal for the clock recovery apparatus is referred to as data clock, while an actual clock signal is referred to as recovered clock signal.
In the signal reproduction apparatus such as hard disk drive or magnetic tape drive, a signal reproduced from a recording medium is supplied as an incoming signal. In such an apparatus, a PRML (Partial Response Maximum Likelihood) method is applied to record and reproduce digital data. In the signal reproduction apparatus applying the PRML method therein, the reproduction signal is first subjected to partial response equalization and then to most likelihood decoding by going through a Viterbi decoder, for example. In this manner, digital data recorded on the recording medium is reproduced. A description is provided next about a conventional reproduction signal processing part of the signal reproduction apparatus applying the PRML method therein. In FIGS. 19 and 20, a thinner arrow-headed signal line indicates an analog signal or a one-bit digital signal, while a thicker arrow-headed signal line indicates a digital signal including two or more bits.
FIG. 19 is a block diagram showing the structure of a reproduction signal processing part into which a first conventional clock recovery apparatus is incorporated. Such structure is found exemplarily in Jenn-Gang Chem, et al. xe2x80x9cAn EPRML Digital Read/Write Channel ICxe2x80x9d 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, SA19.4 (February 1997). In the reproduction signal processing part shown in FIG. 19, a reference numeral 101 denotes the clock recovery apparatus. A reproduction signal 10 is a signal reproduced from a recording medium such as magnetic disk or magnetic tape. On the reproduction signal 10, digital data synchronized with a data clock is presumably recorded. The reproduction signal 10 is amplified in a reproduction amplifier 2, and the amplified signal is subjected to partial response equalization in an equalizer 3. An output signal from the equalizer 3 is forwarded to an AD converter 4, and is sampled and quantized therein with timing of a recovered clock signal 11 to be a decoder input signal 12. The decoder input signal 12 is subjected to most likelihood decoding in a Viterbi decoder 5 according to Viterbi algorithm, and a result obtained thereby is outputted as reproduction data 13. The reproduction data 13 is regarded as data reproduced by the signal reproduction apparatus.
The decoder input signal 12 is forwarded also to a phase error detector 6. Being provided with the decoder input signal 12, the phase error detector 6 outputs a phase error signal 14 to a DA converter 7. The phase error signal 14 indicates a difference in phase (hereinafter, phase error) between the data clock and the recovered clock signal 11. The phase error signal 14 is converted to an analog signal by the DA converter 7. The analog signal is then forwarded to a loop filter 8 to be an oscillation control signal 15. The oscillation control signal 15 is forwarded to a VCO (Voltage Controlled Oscillator) 9. The VCO 9 oscillates according to a frequency controlled by the oscillation control signal 15, and generates the recovered clock signal 11. The recovered clock signal 11 is used as a sampling clock in the AD converter 4. In the first conventional clock recovery apparatus 101, the recovered clock signal 11 phase-locked to the data clock is generated by a PLL (Phase Locked Loop) circuit by a feed-back loop including the AD converter 4, the phase error detector 6, the DA converter 7, the loop filter 8, and the VCO 9.
In the first conventional clock recovery apparatus 101, the equalizer 3 where partial response equalization is performed on the reproduction signal is an analog circuit. For equalization processing with high accuracy and no adjustment, or in an LSI chip, a digital equalizer is preferable. FIG. 20 is a block diagram showing the structure of a reproduction signal processing part into which a second conventional clock recovery apparatus is incorporated. In the reproduction signal processing part shown in FIG. 20, a reference numeral 102 denotes the clock recovery apparatus. Herein, unlike the first conventional clock recovery apparatus 101 where the analog equalizer 3 performs, partial response equalization before AD conversion, a digital equalizer 16 performs partial response equalization after AD conversion. In the second conventional clock recovery apparatus 102, the recovered-clock signal 11 phase-locked to the data clock is generated by a PLL circuit structured by a feed-back loop including the AD converter 4, the equalizer 16, the phase error detector 6, the DA converter 7, the loop filter 8, and the VCO 9.
It is preferable, for the PLL circuit in such a clock recovery apparatus, that a range of the maximum difference in frequency between the data clock and the recovered clock signal 11 (hereinafter, pull-in range) is wider. With a wide pull-in range, these two clocks come to be locked even if not being locked at first. The problem herein is, although being structurally more preferable than the first clock recovery apparatus 101, the clock recovery apparatus 102 has a considerably narrower pull-in range. The reason is as follows: since the equalizer 16 is a digital circuit, the equalizer 16 internally delays the signal 17 on a clock period basis, and accordingly comprehensive delay in the feed-back loop in the PLL circuit is increased. Consequently, the recovered clock signal 11 is delayed being controlled by a phase error between the data clock and the recovered clock signal 11. Such problem becomes evident in the magnetic tape drive where frequency variation of the reproduction signal is wide. Consequently, such a magnetic tape drive cannot employ the second structure in FIG. 20, and thus the equalization processing therein cannot be highly accurate or adjustment-free, or carried out in an LSI chip.
Therefore, an object of the present invention is to provide a clock recovery apparatus whose pull-in range remains wider even if a delay in a feed-back loop in a PLL circuit is lengthened. Further, another object of the present invention is to provide a clock recovery apparatus, with a wider pull-in range, being capable of performing partial response equalization in digital processing, and equalization processing with high accuracy, no adjustment, and in an LSI chip.
The present invention has the following features to attain the objects above.
A first aspect of the present invention is directed to a clock recovery apparatus for recovering a clock signal used to reproduce digital data from an incoming signal, the device comprising: an oscillation part for receiving a control signal, and generating, as an oscillation clock signal, a clock signal whose frequency is based on the control signal; a sampling part for sampling the incoming signal with timing of the oscillation clock signal, and outputting a sampled value of the incoming signal; a phase error detection part for detecting, based on the sampled value, a phase error between the oscillation clock signal and an ideal clock signal used to reproduce the digital data; a quality judgement part for judging quality of the sampled incoming signal by referring to the sampled value; a phase-frequency error detection part for outputting a phase-frequency error signal based on the phase error and the quality judged by the quality judgement part; and a filter part for smoothing the phase-frequency error signal for output to the oscillation part as the control signal, wherein the oscillation clock signal is outputted as the clock signal used to reproduce the digital data.
As described above, in the first aspect, the frequency of the oscillation clock signal is controlled according to the phase error obtained by the phase error detection part and the phase-frequency error obtained from the judgement made by the quality judgement part. In this manner, it becomes possible to provide a clock recovery apparatus with a wider pull-in range, in which the data clock and the recovered clock signal differing in frequency coincide with each other in both frequency and phase. Further, since a digital equalizer can be provided in the feed-back loop in the PLL circuit, the equalization processing in the clock recovery apparatus can be highly accurate, adjustment-free, or carried out in an LSI chip.
According to a second aspect, in the first aspect, the quality judgement part comprises: a temporary judgement part for estimating the digital data based on the sampled value for output as a temporary judgement result; a reference value generation part for generating a reference value based on the temporary judgement result; and a calculation part for calculating a difference between the sampled value and the reference value, wherein the quality is judged according to the difference.
As described above, in the second aspect, the signal quality can be judged according to the difference between the sampled value and the reference value based on the sampled value.
According to a third aspect, in the second aspect, the reference value generation part generates the reference value which is corresponding to a change in amplitude of the sampled incoming signal.
As described above, in the third aspect, the reference value in the quality judgement part changes corresponding to the change in amplitude of the incoming signal. Therefore, it becomes possible to provide a recovery clock device in which the data clock and the recovered clock signal coincide with each other in both frequency and phase even if the amplitude of the incoming signal varies to a greater degree with the passage of time.
According to a fourth aspect, in the second aspect, the quality judgement part compares a value based on an absolute value of the difference with a given threshold value, and accordingly judges the quality.
As described above, in the fourth aspect, the signal quality can be judged according to the absolute value of the difference between the sampled value and the reference value based on the sampled value.
According to a fifth aspect, in the second aspect, the quality judgement part compares a value based on a square of the difference with a given threshold value, and accordingly judges the quality.
As described above, in the fifth aspect, the signal quality can be judged according to the square of the difference between the sampled value and the reference value based on the sampled value.
According to a sixth aspect, in the second aspect, the quality judgement part includes a low pass filter, compares a value obtained after the difference goes through the low pass filter with a given threshold value, and accordingly judges the quality.
As described above, in the sixth aspect, the quality of the incoming signal is judged according to a value obtained after the difference goes through the low pass filter. Therefore, it becomes possible to provide a clock recovery apparatus in which the data clock and the recovered clock signal coincide with each other, with accuracy, in both frequency and phase without being affected by any noise supposedly included in the incoming signal.
According to a seventh aspect, in the first aspect, according to the judgement made by the quality judgement part, the phase-frequency error detection part takes in, for retention, a sign of the phase error every time the quality changes from good to bad, and when the quality is good, outputs the phase error, but when the quality is bad, outputs a given error value corresponding to the-retained sign.
As described above, in the seventh aspect, the error value is equal to the given value which is determined by a sign retained when the quality changed to be bad. Therefore, it becomes possible to provide a clock recovery apparatus in which the data clock and the recovered clock signal coincide with each other, with accuracy, both in frequency and phase.
According to an eighth aspect, in the first aspect, the phase-frequency error detection part includes a phase error filter part for smoothing the phase error, and takes in, for retention, a sign of an output signal of the phase error filter part every time the quality changes from good to bad, and when the quality is good, outputs the phase error, but when the quality is bad, outputs a given error value corresponding to the retained sign.
As described above, in the eighth aspect, the quality of the incoming signal is judged according to the phase error after the phase error filter part. Therefore, it becomes possible to provide a clock recovery apparatus in which the data clock and the recovered clock signal coincide with each other, with accuracy, in both frequency and phase without being affected by any noise supposedly included in the incoming signal.
According to a ninth aspect, in the first aspect, the phase-frequency error detection part includes a phase error filter part for smoothing the phase error, and according to the judgement made by the quality judgement part, takes in, for retention, a sign of an output signal of the phase error filter part every time the quality changes from good to bad, and when the quality is good, outputs the phase error, but when the quality is bad, outputs a given error value according to the retained sign for a given duration of time right after the quality is judged as being bad.
As described above, in the ninth aspect, the quality of the incoming signal is judged according to the phase error after the phase error filter part. Therefore, it becomes possible to provide a clock recovery apparatus in which the data clock and the recovered clock signal coincide with each other, with accuracy, in both frequency and phase without being affected by any noise supposedly included in the incoming signal. Further, therein, the frequency of the recovered clock signal may not be erroneously shifted to a greater degree from that of the data clock. This is because, the duration of the quality being bad is limited to a given time.
According to a tenth aspect, in the first aspect, the filter part includes an integration part for integrating the phase-frequency error signal outputted from the phase-frequency error detection part.
As described above, in the tenth aspect, it becomes possible to provide a clock recovery apparatus in which the frequency of the recovered clock signal generated by the oscillation part gradually changes with respect to the change of the detected phase-frequency error.
According to an eleventh aspect, in the first aspect, the sampling part includes an equalization part for equalizing the incoming signal sampled by the oscillation clock signal for output as the sampled value.
As described above, in the eleventh aspect, it becomes possible to provide a clock recovery apparatus which can be incorporated into a signal reproduction processing part in the signal reproduction apparatus applying PRML method.
A twelfth aspect is directed to a clock recovery apparatus for recovering a clock signal used to reproduce digital data from an incoming signal, the device comprising: an oscillation part for receiving a control signal, and generating, as an oscillation clock signal, a clock signal whose frequency is based on the control signal; a sampling part for sampling the incoming signal with timing of the oscillation clock signal, and outputting a sampled value of the incoming signal; a phase error detection part for detecting, based on the sampled value, a phase error between the oscillation clock signal and the clock signal used to reproduce the digital data; a frequency error detection part for detecting a difference between a frequency of the oscillation clock signal and a given reference frequency as a frequency error; a phase-frequency error detection part for outputting a phase-frequency error signal based on the phase error and the frequency error; and a filter part for smoothing the phase-frequency error signal for output to the oscillation part as the control signal, wherein the oscillation clock signal is outputted as the clock signal used to reproduce the digital data.
As described above, in the twelfth aspect, the frequency of the oscillation clock signal is controlled according to the phase error obtained by the phase error detection part and the phase-frequency error obtained from the frequency error outputted from the frequency error detection part. In this manner, it becomes possible to provide a clock recovery apparatus whose pull-in range is wider than the first aspect, and accordingly the effects by the first aspect becomes more apparent.
According to a thirteenth aspect, in the twelfth aspect, when an absolute value of the frequency error is larger than a given threshold value, the phase-frequency error detection part outputs a given error value having a sign identical to that of the frequency error, and when the absolute value of the frequency error is smaller than the threshold value, the phase-frequency error detection part outputs the phase error.
As described above, in the thirteenth aspect, when the absolute value of the frequency error is larger than the given threshold value, the frequency of the oscillation clock signal is controlled according to the given error value having a sign identical to that of the frequency error. Therefore, a clock recovery apparatus can be provided, in which the data clock and the recovered clock signal coincide with each other, with accuracy, in both frequency and phase.
According to a fourteenth aspect, in the twelfth aspect, the frequency error detection part includes a count part for counting the oscillation clock signals generated during a given time, and outputs a difference between a count value obtained by the count part and a given expected value as the frequency error.
As described above, in the fourteenth aspect, the frequency error can be detected with high accuracy. Accordingly, a clock recovery apparatus can be provided, in which the data clock and the recovered clock signal coincide with each other, with accuracy, in both frequency and phase.
According to a fifteenth aspect, in the twelfth aspect, the filter part includes an integration part for integrating the phase-frequency error signal outputted from the phase-frequency error detection part.
As described above, in the fifteenth aspect, it becomes possible to provide a clock recovery apparatus in which the frequency of the recovered clock signal generated by the oscillation part gradually changes with respect to the change of the detected phase-frequency error.
According to a sixteenth aspect, in the twelfth aspect, the sampling part includes an equalization part for equalizing the incoming signal sampled by the oscillation clock signal for output as the sampled value.
As described above, in the sixteenth aspect, it becomes possible to provide a clock recovery apparatus which can be incorporated into a signal reproduction processing part in the signal reproduction apparatus applying PRML method.
A seventeenth aspect of the present invention is directed to a clock recovery apparatus for recovering a clock signal used to reproduce digital data from an incoming signal, the device comprising: an oscillation part for receiving a control signal, and generating, as an oscillation clock signal, a clock signal whose frequency is based on the control signal; a sampling part for sampling the incoming signal with timing of the oscillation clock signal, and outputting a sampled value of the incoming signal; a phase error detection part for detecting, based on the sampled value, a phase error between the oscillation clock signal and the clock signal used to reproduce the digital data; a quality judgement part for judging quality of the sampled incoming signal by referring to the sampled value; a frequency error detection part for detecting a difference between a frequency of the oscillation clock signal and a given reference frequency as a frequency error; a phase-frequency error detection part for outputting a phase-frequency error signal based on the phase error, the quality judged by the quality judgement part, and the frequency error; and a filter part for smoothing the phase-frequency error signal for output to the oscillation part as the control signal, wherein the oscillation clock signal is outputted as the clock signal used to reproduce the digital data.
As described above, in the seventeenth aspect, the frequency of the oscillation clock signal is controlled according to the phase error obtained by the phase error detection part, the judgement made by the quality judgement part, and the frequency error obtained by the frequency error detection part. In this manner, it becomes possible to provide a clock recovery apparatus whose pull-in range is wider than the first aspect, and in which the frequency error detection part can be easily implemented.
According to an eighteenth aspect, in the seventeenth aspect, the quality judgement part comprises: a temporary judgement part for estimating the digital data based on the sampled value for output as a temporary judgement result; a reference value generation part for generating a reference value based on the temporary judgement result; and a calculation part for calculating a difference between the sampled value and the reference value, wherein the quality is judged according to the difference.
As described above, in the eighteenth aspect, the signal quality can be judged according to the difference between the sampled value and the reference value based on the sampled value.
According to a nineteenth aspect, in the eighteenth aspect, the reference value generation part generates the reference value which is corresponding to a change in amplitude of the sampled incoming signal.
As described above, in the nineteenth aspect, the reference value in the quality judgement part changes corresponding to the change in amplitude of the incoming signal. Therefore, it becomes possible to provide a recovery clock device in which the data clock and the recovered clock signal coincide with each other in frequency and phase even if the amplitude of the incoming signal varies to a greater degree with the passage of time.
According to a twentieth aspect, in the eighteenth aspect, the quality judgement part compares a value based on an absolute value of the difference with a given threshold value, and accordingly determines the quality.
As described above, in the twentieth aspect, the signal quality can be judged according to the absolute value of the difference between the sampled value and the reference value based on the sampled value.
According to a twenty-first aspect, in the eighteenth aspect, the quality judgement part compares a value based on a square of the difference with a given threshold value, and accordingly determines the quality.
As described above, in the twenty-first aspect, the signal quality can be judged according to the square of the difference between the sampled value and the reference value based on the sampled value.
According to a, twenty-second aspect, in the eighteenth aspect, the quality judgement part includes a low pass filter, compares a value obtained after the difference goes through the low pass filter with a given threshold value, and accordingly judges the quality.
As described above, in the twenty-second aspect, the quality of the incoming signal is judged according to a value obtained after the difference goes through the low pass filter. Therefore, it becomes possible to provide a clock recovery apparatus in which the data clock and the recovered clock signal coincide with each other, with accuracy, in both frequency and phase without being affected by any noise supposedly included in the incoming signal.
According to a twenty-third aspect, in the seventeenth aspect, according to the judgement made by the quality judgement part, the phase-frequency error detection part takes in, for retention, a sign of the phase error every time the quality changes from good to bad, and when an absolute value of the frequency error is larger than a given threshold value, outputs a given first error value having a sign identical to that of the frequency error, but when the absolute value of the frequency error is smaller than the threshold value, outputs the phase error for a duration of the quality being good, and for a duration of the quality being bad, outputs a given second error value according to the retained sign.
As described above, in the twenty-third aspect, when the absolute value of the frequency error is larger than the given threshold value, the operation is similar to the thirteenth aspect, and if the absolute value of the frequency error becomes smaller than the given threshold value, the operation becomes similar to the seventh aspect. In this manner, it becomes possible to provide a recovery clock device in which the data clock and the recovered clock signal coincide with each other, with accuracy, in frequency and phase.
According to a twenty-fourth aspect, in the seventeenth aspect, the phase-frequency error detection part includes a phase error filter part for smoothing the phase error, and according to the judgement made by the quality judgement part, takes in, for retention, a sign of an output signal of the phase error filter part every time the quality changes from good to bad, and when an absolute value of the frequency error is larger than a given threshold value, outputs a given first error value having a sign identical to that of the frequency error, but when the absolute value of the frequency error is smaller than the threshold value, outputs the phase error for a duration of the quality being good, and for a duration of the quality being bad, outputs a given second error value according to the retained sign.
As described above, in the twenty-fourth aspect, when the absolute value of the frequency error is larger than the given threshold value, the operation is similar to the thirteenth aspect, and if the absolute value of the frequency error becomes smaller than the given threshold value, the operation becomes similar to the eighth aspect. In this manner, it becomes possible to provide a recovery clock device in which the data clock and the recovered clock signal coincide with each other, with accuracy, in frequency and phase without being affected by any noise supposedly included in the incoming signal.
According to a twenty-fifth aspect, in the seventeenth aspect, the phase-frequency error detection part includes a phase error filter part for smoothing the phase error, and according to the judgement made by the quality judgement part, takes in, for retention, a sign of an output signal of the phase error filter part every time the quality changes from good to bad, and when an absolute value of the frequency error is larger than a given threshold value, outputs a given first error value having a sign identical to that of the frequency error, but when the absolute value of the frequency error is smaller than the threshold value, outputs the phase error for a duration of the quality being good, and for a duration of the quality being bad, outputs a given second error value according to the retained sign only for a given duration of time right after the quality is judged as being bad.
As described above, in the twenty-fifth aspect, when the absolute value of the frequency error is larger than the given threshold value, the operation is similar to the thirteenth aspect, and if the absolute value of the frequency error becomes smaller than the given threshold value, the operation becomes similar to the ninth aspect. In this manner, without being affected by any noise supposedly included in the incoming signal, the frequency of the recovered clock signal may not erroneously shifted to a greater degree from that of the data clock. Accordingly, it becomes possible to provide a clock recovery apparatus in which the data clock and the recovered clock signal coincide with each other, with accuracy, in both frequency and phase.
According to a twenty-sixth aspect, in the seventeenth aspect, the frequency error detection part includes a count part for counting the oscillation clock signals generated during a given time, and outputs a difference between a count value obtained by the count part and a given expected value as the frequency error.
As described above, in the twenty-sixth aspect, the frequency error can be detected with high accuracy. Accordingly, a clock recovery apparatus can be provided, in which the data clock and the recovered clock signal coincide with each other, with accuracy, in both frequency and phase.
According to a twenty-seventh aspect, in the seventeenth aspect, the filter part includes an integration part for integrating the phase-frequency error signal from the phase-frequency error detection part.
As described above, in the twenty-seventh aspect, it becomes possible to provide a clock recovery apparatus in which the frequency of the recovered clock signal generated by the oscillation part gradually changes with respect to the change of the detected phase-frequency error.
According to a twenty-eighth aspect, in the seventeenth aspect, the sampling part includes an., equalization part for equalizing the, incoming signal sampled by the oscillation clock signal for output as the sampled value.
As described above, in the twenty-eighth aspect, it becomes possible to provide a clock recovery apparatus which can be incorporated into a signal reproduction processing part in the signal reproduction apparatus applying PRML method.
A twenty-ninth aspect of the present invention is directed to a clock recovery apparatus for recovering a clock signal used to reproduce digital data from an incoming signal, the device comprising: an oscillation part for receiving a control signal, and generating, as an oscillation clock signal, a clock signal whose frequency is based on the control signal; a sampling part for sampling the incoming signal with timing of the oscillation clock signal, and outputting a sampled value of the incoming signal; a phase error detection part for detecting, based on the sampled value, a phase error between the oscillation clock signal and the clock signal used to reproduce the digital data; a frequency error detection part for detecting a difference between a frequency of the oscillation clock signal and a given reference frequency as a frequency error; a selection part for selecting the phase error when an absolute value of the frequency error is smaller than a given threshold value, and selects the frequency error when the absolute value of the frequency error is larger than the threshold value; an integration part for integrating an output of the selection part; and an addition part for adding the phase error from the phase error detection part and an output of the integration part for output as the control signal to the oscillation part, wherein the oscillation clock signal is outputted as the clock signal used to reproduce the digital data.
As described above, in the twenty-ninth aspect, when the absolute value of the frequency error obtained by the frequency error detection part is larger than the given threshold value, the frequency of the oscillation clock signal is controlled by, instead of the phase error obtained by the phase error detection part, the signal in which the result obtained by integrating the frequency error and the output signal from the phase error detection part are added. Accordingly, it becomes possible to provide a clock recovery apparatus whose pull-in range is wider than the first aspect, and in which the data clock and the recovered clock signal coincide with each other in frequency and phase in a shorter time.
According to a thirtieth aspect, in the twenty-ninth aspect, the frequency error detection part includes a count part for counting the oscillation clock signals generated during a given time, and regards a difference between a count value obtained by the count part and a given expected value as the frequency error.
As described above, in the thirtieth aspect, the frequency error can be detected with high accuracy. Accordingly, a clock recovery apparatus can be provided, in which the data clock and the recovered clock signal coincide with each other, with accuracy, in both frequency and phase.
According to a thirty-first aspect, in the twenty-ninth aspect, the sampling part includes an equalization part for equalizing the incoming signal sampled by the oscillation clock signal for output as the sampled value.
As described above, in the thirty-first aspect, it becomes possible to provide a clock recovery apparatus which can be incorporated into a signal reproduction processing part in the signal reproduction apparatus applying PRML method.
A thirty-second aspect of the present invention is directed to a clock recovery apparatus for recovering a clock signal used to reproduce digital data from an incoming signal, the device comprising: an oscillation part for receiving a control signal, and generating, as an oscillation clock signal, a clock signal whose frequency is based on the control signal; a sampling part for sampling the incoming signal with timing of the oscillation clock signal, and outputting a sampled value of the incoming signal; a phase error detection part for detecting, based on the sampled value, a phase error between the oscillation clock signal and the clock signal used to reproduce the digital data; a quality judgement part for judging quality of the sampled incoming signal by referring to the sampled value; a phase-frequency error detection part for outputting a phase-frequency error signal based on the phase error and the quality judged by the quality judgement part; a frequency error detection part for detecting a difference between a frequency of the oscillation clock signal and a given reference frequency as a frequency error; a selection part for selecting the phase-frequency error signal when an absolute value of the frequency error is smaller than a given threshold value, and selects the frequency error when the absolute value of the frequency error is larger than the threshold value; an integration part for integrating an output of the selection part; and an addition part for adding the phase-frequency error signal from the phase-frequency error detection part and an output of the integration part for output as the control signal to the oscillation part, wherein the oscillation clock signal is outputted as the clock signal used to reproduce the digital data.
As described above, in the thirty-second aspect, when the absolute value of the frequency error obtained by the frequency error detection part is larger than the given threshold value, the frequency of the oscillation clock signal is controlled by, instead of the phase error obtained by the phase error detection part and the judgement made by the quality judgement part, the signal obtained by adding the result obtained by integrating the frequency error and the output signal from the phase-frequency error detection part. Accordingly, it becomes possible to provide a clock recovery apparatus whose pull-in range is wider than the first aspect, and in which the data clock and the recovered clock signal coincide with each other in frequency and phase in a shorter time, and the frequency error detection part can be easily implemented.
According to a thirty-third aspect, in the thirty-second aspect, the quality judgement part comprises: a temporary judgement part for estimating the digital data based on the sampled value for output as a temporary judgement result; a reference value generation part for generating a reference value based on the temporary judgement result; and a calculation part for calculating a difference between the sampled value and the reference value, wherein the quality is judged according to the difference.
As described above, in the thirty-third aspect, the signal quality can be judged according to the difference between the sampled value and the reference value based on the sampled value.
According to a thirty-fourth aspect, in the thirty-third aspect, the reference value generation part generates the reference value which is corresponding to a change in amplitude of the sampled incoming signal.
As described above, in the thirty-fourth aspect, the reference value in the quality judgement part changes corresponding to the change in amplitude of the incoming signal. Therefore, it becomes possible to provide a recovery clock device in which the data clock and the recovered clock signal coincide with each other in frequency and phase even if the amplitude of the incoming signal varies to a greater degree with the passage of time.
According to a thirty-fifth aspect, in the thirty-third aspect, the quality judgement part compares a value based on an absolute value of the difference with a given threshold value, and accordingly determines the quality.
As described above, in the thirty-fifth aspect, the signal quality can be judged according to the absolute value of the difference between the sampled value and the reference value based on the sampled value.
According to a thirty-sixth aspect, in the thirty-third aspect, the quality judgement part compares a value based on a square of the difference with a given threshold value, and accordingly determines the quality.
As described above, in the thirty-sixth aspect, the signal quality can be judged according to the square of the difference between the sampled value and the reference value based on the sampled value.
According to a thirty-seventh aspect, in the thirty-third aspect, the quality judgement part includes a low pass filter, compares a value obtained after the difference goes through the low pass filter with a given threshold value, and accordingly judges the quality.
As described above, in the thirty-seventh aspect, the quality of the incoming signal is judged based on a difference obtained after the difference goes through the low pass filter. In this manner, it becomes possible to provide a clock recovery apparatus in which the data clock and the recovered clock signal coincide with each other, with accuracy, in both frequency and phase without being affected by any noise supposedly included in the incoming signal.
According to a thirty-eighth aspect, in the thirty-second aspect, according to the judgement made by the quality judgement part, the phase-frequency error detection part takes in, for retention, a sign of the phase error every time the quality changes from good to bad, and outputs the phase error when the quality is good but outputs a given error value corresponding to the retained sign when the quality is bad.
As described above, in the thirty-eighth aspect, the error value is equal to the given value which is determined by a sign retained when the quality changed to be bad. Therefore, it become possible to provide a clock recovery apparatus in which the data clock and the recovered clock signal coincide with each other, with accuracy, both in frequency and phase.
According to a thirty-ninth aspect, in the thirty-second aspect, the phase-frequency error detection part includes a phase error filter part for smoothing the phase error, and according to the judgement made by the quality judgement part, takes in, for retention, a sign of an output signal of the phase error filter part every time the quality changes from good to bad, and when the quality is good, outputs the phase error, but when the quality is bad, outputs a given error value corresponding to the retained sign.
As described above, in the thirty-ninth aspect, the quality of the incoming signal is judged according to the phase error after the phase error filter part. Therefore, it becomes possible to provide a clock recovery apparatus in which the data clock and the recovered clock signal coincide with each other, with accuracy, in both frequency and phase without being affected by any noise supposedly included in the incoming signal.
According to a fortieth aspect, in the thirty-second aspect, the phase-frequency error detection part includes a phase error filter part for smoothing the phase error, and according to the judgement made by the quality judgement part, takes in, for retention, a sign of an output signal of the phase error filter part every time the quality changes from good to bad, and when the quality is good, outputs the phase error, but when the quality is bad, outputs a given error value according to the retained sign for a given duration of time right after the quality is judged as being bad.
As described above, in the fortieth aspect, the quality of the incoming signal is judged according to the phase error after the phase error filter part. Therefore, it becomes possible to provide a clock recovery apparatus in which the data clock and the recovered clock signal coincide with each other, with accuracy, in both frequency and phase without being affected by any noise supposedly included in the incoming signal. Further, therein, the frequency of the recovered clock signal may not be erroneously shifted to a greater degree from that of the data clock. This is because, the duration of the quality being bad is limited to a given time.
According to a forty-first aspect, in the thirty-second aspect, the frequency error detection part includes a count part for counting the oscillation clock signals generated during a given time, and outputs a difference between a count value obtained by the count part and a given expected value as the frequency error.
As described above, in the forty-first aspect, the frequency error can be detected with high accuracy. Accordingly, a clock recovery apparatus can be provided, in which the data clock and the recovered clock signal coincide with each other, with accuracy, in both frequency and phase.
According to a forty-second aspect, in the thirty-second aspect, the sampling part includes an equalization part for equalizing the incoming signal sampled by the oscillation clock signal for output as the sampled value.
As described above, in the forty-second aspect, it becomes possible to provide a clock recovery apparatus which can be incorporated into a signal reproduction processing part in the signal reproduction apparatus applying PRML method.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.